1. Technical Field
The present invention relates to an output apparatus and a test apparatus.
2. Related Art
A current output type DA conversion apparatus is known. A current output type DA conversion apparatus includes a plurality of current sources, and a plurality of switches for switching connection between each of the plurality of current sources and the output end. The current output type DA conversion apparatus switches current of the plurality of current sources corresponding to the input data, to supply the current corresponding to the input data to the output end.
The following are prior art documents.    Patent Document No. 1: U.S. Pat. No. 6,664,906    Patent Document No. 2: Japanese Patent Application Publication No. 2003-115761    Patent Document No. 3: Japanese Patent Application Publication No. 2007-227990    Patent Document No. 4: Japanese Patent Application Publication No. H06-132821    Patent Document No. 5: Japanese Patent No. 2974377
However, a current output type DA conversion apparatus causes glitch noise in the output current, if switching timing is different among the plurality of switches. For example, suppose that a DA conversion apparatus having four switches is provided with input data for switching the four switches from the state of “1000” to the state of “0111.” In this case, the switching timing of the most significant bit is slower than the other bits, the state transition of the four switches will be “1000”→“1111”→“0111.” Therefore, the DA conversion apparatus will cause large glitch noise in the intermediate state where the four switches are brought into the state of “1111.”
Patent Document No. 1 and Patent Document No. 2 disclose a circuit in which on/off skew of a differential switch is reduced using SR latch. The circuit disclosed in Patent Document No. 1 and Patent Document No. 2, however, cannot reduce the skew between pieces of data.
Patent Document No. 3 discloses a circuit that changes timings of logic for driving a switch, to reduce the glitch noise. However, with the circuit disclosed in Patent Document No. 3, the timing can only be adjusted within the range of the delay control of inverters.
Patent Document No. 4 discloses a circuit for canceling out glitch noise caused in a DAC using a signal generated by another DAC. The circuit disclosed in Patent Document No. 4, however, has to be equipped with an additional high-speed DAC, and further to perform operation, which inhibits high-speed operation.
Patent Document No. 5 discloses a circuit that simulates the glitch noise occurring in a DAC using a pulse current, to cancel it out in the later stages. However, the circuit disclosed in Patent Document No. 5 has to additionally include a high-speed pulse generator, and further to operate the adder in high speed.
As explained above, the circuits disclosed in Patent Documents No. 1-No. 5 cannot assuredly reduce glitch noise of a current output type DA conversion apparatus, unless using an additional high-speed circuit.